1. Field of the Invention
The present invention is directed toward an improved manufacturing process for a producing a high speed PN photodiode having a distributed photodiode structure and the resulting photodiode.
2. Description of the Related Art
Photodiodes are diodes in which charge carriers are generated responsive to light incident upon the photodiode. Any PN junction diode which admits light can function as a photodiode. A photodiode outputs voltage or current when absorbing light. In a photodiode which is intended for high speed communication systems, it is important to optimize the performance for light conversion efficiency, speed (minimal transit time delay), minimum RC time constant, ability to operate at low reverse bias voltage, and cost in the application in which the photodiode will be employed.
The structure of a conventional discrete PIN photodiode 24 is illustrated in FIG. 1B. A wafer 50 is lightly doped with N dopant in order to produce an intrinsic region 56. A P+ region 52 is formed on one surface of the wafer and an N+ region 58 is formed on the opposing surface of wafer 50 with intrinsic region 56 interposed P+ region 52 and N+ region 58. A reflective layer 60, typically gold, is disposed on the surface containing P+ region 58 with reflective layer 60 also serving as the electrical contact to N+ region 58. A metal contact 54 is disposed on the surface containing P+ region 52 to provide the electrical connection to the P+ region.
Typically, one power supply potential is applied to the reflective layer 60 and another power supply voltage is applied to contact 54 to reverse bias the PN junction formed by P+ region 52 and N+ region 18. This forms a large depletion region within the intrinsic region 56 wherein electron and hole charge carrier pairs generated by light photons incident upon the intrinsic region 56 are rapidly accelerated toward the P+ and N+ regions respectively by the electric field of the reverse bias voltage. Charge carrier pairs are also typically generated outside the depletion region within intrinsic region 56 which diffuse, due to random thermal motion of the carriers, at a much slower velocity until they reach either the depletion region or the junction formed by P+ region 52 and intrinsic region 56 of photodiode 24.
A conventional photodiode that is designed for high quantum, i.e. light conversion, efficiency requires that the light path within the photo current collection zone, i.e. the depletion and non-depletion zones within intrinsic region 56, be sufficient in length so that most of the light photons of the incident light signal area are absorbed and converted into electron-hole pairs that are collectable at the P+ and N+ regions. Usually, this requires that the width of the intrinsic region 56, which is the primary light collection region, be several times the length required for light absorption. If diode 10 has an efficient back-side reflector, such as reflective layer 60, which effectively doubles the light path within diode 24, then the intrinsic region 56 of the photodiode can be made narrower. For a typical near infrared silicon photodiode, the nominal absorption path length is about 15-25 microns. The path length should be at least two to three times the nominal absorption path length to obtain good light conversion efficiency.
Wafer 50 can be lapped to as thin as 100 microns in order to obtain a thinner intrinsic region 56 and better performance for the resulting PIN photodiode. However, it is generally not practical to thin wafers beyond this limit without an excessive level of wafer breakage along with severe wafer handling and processing problems. As noted above, however, the width of intrinsic region 56 that is optimal for the performance of the photodiode can be as little as 30 microns.
A photodiode designed for high frequency response requires that the photo current pairs generated by the light signal be collected rapidly and that the diode RC time constant is fast. Rapid photo current pair collection usually requires that most of the photo current pairs generated by the light signal be generated with the depletion region formed by the reverse bias voltage because the pairs will have a high drift velocity. Otherwise, the photo generated charge carrier pairs produced in the non-depletion regions within intrinsic region 56 and within diffusion distance of the collection electrodes 52 and 58 will have a diffusion velocity that is several hundred times slower than the velocity of the pairs generated within the depletion zone. The photo generated charge carrier pairs in the non-depletion zones will slowly migrate for collection at P+ region 52 and N+ region 58 resulting in a tall on the trailing edge of the electrical signal corresponding to the light signal. The diffusion distance of the charge carriers is determined by the carrier mean free path before re-combination and may exceed 150 microns.
A fast RC time constant for photodiode 24 requires minimal capacitance and low series resistance between the electrical contacts 54 and 60 and the photo current pair collection sites at the margin between P+ region 52 and the depletion zone and the margin between N+ region 58 and the depletion zone. The greater the width of the intrinsic region 56, the greater the width of the depletion zone and the lower the capacitance per unit area of photodiode 24. Since the width of the depletion zone increases with the magnitude of the reverse bias voltage, it is typical for high speed photodiodes to have a relatively high reverse voltage applied to them.
The inclusion of lightly doped intrinsic region 56 between the P+ and N+ regions 52 and 58 results in a PIN photodiode with a wider depletion region, depending on the magnitude of the reverse bias voltage, which improves the light collection efficiency, increases speed, and reduces capacitance over that of a simple PN diode structure.
The PIN photodiode is typically produced by diffusing the N+ region 58 on the back side of the lightly doped (N) wafer 50, diffusing the P+ region 52 on the topside of the wafer 50, and then adding metal contacts to each side of the wafer. Typically, the backside contact area connected to N+ region 58 is reflective layer 60 and is made of gold. The reflective layer is then typically connected to the ground voltage terminal.
Although a PIN photodiode outperforms a standard PN diode, the PIN photodiode structure cannot be easily manufactured by standard semiconductor processes wherein fabrication is typically performed on only one side of the semiconductor wafer 50. In typical high volume applications, it is now standard practice to fabricate the receiver circuitry and transmitter driver in a single integrated circuit (IC) to produce a transceiver IC. As described above, it is difficult to integrate an efficient photodiode on the same semiconductor substrate as the transceiver circuit. As a result, a discrete infrared photodiode is typically assembled with the transceiver circuit and an LED, along with lenses for the photodiode and LED, into a plastic molded package to form a transceiver module. The transceiver module is designed to be small in size and allow placement in the incorporating electronic device so as to have a wide angle of view, typically through an infrared window on the transceiver casing. The transceiver IC is designed to digitally interface to some type of serial data communications device such as an Infrared Communication Controller (ICC), UART, USART, or a microprocessor performing the same function.
As noted above, any PN junction diode which admits light can function as a photodiode. A PN diode junction can also be fabricated using standard IC processes. However, the photo-current collection region within an electric field, the drift region, in a PN photodiode is limited to the relatively thin depletion zone produced when the PN junction is reverse biased. This thin drift region is much less efficient in the collection of photo-generated charge carrier pairs because most of the pairs are generated outside of the depletion zone. Also, the charge pairs generated outside of the depletion zone thermally diffuse to collection points margins of the P and N layers and into the depletion zone at a much slower relative speed resulting in slow photodiode performance. In addition, the highly doped P and N regions result in high diode capacitance per unit area which further slows the performance of the photodiode.
Accordingly, it is an object of the present invention to produce a PN photodiode having high speed operation.
The present invention describes an improved method for producing a distributed PN diode featuring an arbitrarily thin intrinsic region which can be depleted at a low operating voltage and multiple active regions distributed across a surface of the photodiode.
An embodiment of a method, according to the present invention, for fabricating a distributed PN photodiode includes providing a first semiconductor substrate doped with a first dopant type, the first semiconductor substrate having first and second planar surfaces. The method then calls for bonding a first surface of a second semiconductor substrate to the first planar surface of the first semiconductor substrate and lapping the second planar surface of the first semiconductor substrate. The method then sets forth selectively masking and diffusing a predetermined portion of the second planar surface of the first semiconductor substrate with a second dopant type to form a plurality of second active regions. The method then requires forming a first oxide layer on the second planar surface of the first semiconductor substrate and selectively masking and etching the first oxide layer to form a plurality of contact holes in the first oxide layer, where each contact hole is formed in communication with one of the plurality of second active regions. The method then recites forming a contact that interconnects each of the plurality of contact holes.
In yet another embodiment of a process according to the present invention, a layer is formed on either the first surface of the first semiconductor substrate or the first surface of the second semiconductor substrate. This layer can be an oxide layer, where the thickness of the oxide layer can be controlled to form a dielectric interference reflector, a reflective layer, or a conductive layer.